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</html>";s:4:"text";s:11741:"iPhone 12 mini The second session of the day is on Mobile (aka Notebook) processors. We’ve heard of Baidu’s Kunlun a few months ago due to a press release from the company and Samsung stating that the silicon was making use of Interposer-Cube 2.5D packaging, as well as HBM2, and packing 260 TOPs into 150 W. The talk featuring Alibaba’s Hanguang 800 NPU will also be interesting, as we saw results submitted to MLPerf back in November, though not a lot of information about the chip itself. Hot Chips Organizing Committee, Marketing, General: chair@hotchips.org 12:10PM EDT - We're 20 minutes from the Intel talk starting, but Hot Chips will commence with a 15-minute intro talk to the conference, which we'll cover here, 12:10PM EDT - This is the first 'Virtual' Hot Chips, due to COVID. Hot Chips 2020: Marvell Details ThunderX3 CPUs - Up to 60 Cores Per Die, 96 Dual-Die in 2021 by Andrei Frumusanu on August 17, 2020 4:30 PM … Very interesting price strategy for Europe... @blu51899890 @anandtech @im_renga There is near to no traffic between the GPU - so it's not an issue. $799 mmWave <> €909 sub-6 And whether it's the future of computing, or part of it stuck as security?? Intel’s Sailesh Kothapalli with an Ice Lake Xeon CPU in Dec 2018. @Apocalyptus @IanCutress Working on it... @aik0uka 1st Gen CloudKey user here. The finer details aren’t clear, but for POWER9 the company did implement a new configurable memory system called OMI, so it will be interesting to see if that makes it into the new design. Website: webmaster@hotchips.org, Hot Chips Organizing Committee, Marketing, Hot Chips: A Symposium on High Performance Chips. Aaron Pressman of Fortune recently published a detailed look into Jim Keller, along with comments and quotes from a number of the industry covering his past, his present, and some goals for the future. On behalf of the committee, please take care, and we look forward to planning another interesting event this year! Nothing new in any of those talks, it appears. Best regards, OreoCookie - Wednesday, August 19, 2020 - link @Suzamax I'm not an idiot. If any of the presenters at this years conference wants to get in touch before the event and take us through their presentation in advance, with the potential for a proper article on their disclosures, then please get in contact at ian@anandtech.com. iPhone 12 We have a new format for Hot Chips Symposium this year — the format will be Virtual/Online with potentially an in-person option (to be determined). Posted on May 14, 2020 Today the Hot Chips program committee officially announced the August conference line-up, posted to hotchips.org . The first talk is on Intel’s Agilex generation of FPGAs. Not heard many complains so far (as a silicon person!). Hot Chips Organizing Committee, Marketing Today at Hot Chips 2020, Microsoft will detail more of the internals of the Xbox Series X system architecture. For details send your request to registration@hotchips.org. @chrisheinonen I've heard of a number of complaints lately involving the Troutdale facility. Their Dynamic Neural Accelerator (DNA) architecture and AI hardware and software co-exploration engine enable adaptation of app-specific AI accelerator designs. As with the NVIDIA talk, users looking for consumer graphics related details aren’t likely to find anything specific here. Sponsorship: sponsor@hotchips.org A: It's not base 7nm, it's progressed over time. Bargain, 12:11PM EDT - Tutorials were yesterday, whereas the main conference starts today, 12:12PM EDT - Today there's a lot of talks on CPU and GPU. The keynotes at Hot Chips aren’t necessarily a ground for announcing new items, but with Raja on the stage I expect him to go into more detail about how things have changed at Intel to get into graphics. Interesting that Alibaba, Baidu and Google are present but not Amazon. Or "Plutonium"; 10 nm and below is probably a radioactive subject at Intel right now. @DanMatte I haven’t tried it on the PS4 yet but it runs extremely well on PC and considering the graphics quite well on mobile. The new chip uses 96 custom Arm v8.3+ cores, built on TSMC 7nm, with up to four threads per core. The final talk of the session is again from IBM, this time on the z15 processor line. Sorry Ian, I tried to get an answer about the Xbox Series X's GPU TDP because if the TDP is the same as the Xbox One's GPU (120W at worse) then AMD has a monster of a GPU on their hands. I think his answer about 'TDP is different based on workload' was a massive cop-out and someone disingenuous given what the definition of TDP actually is, and that engineers in the room understand nuance around TDP numbers. 09:35PM EDT - Q: Are you happy as DX12 as a low hardware API? ... Crazyeyeskillah - Monday, August 17, 2020 - link  MS also re-writes the driver and smashes it together, we replace that and the firmware in the GPU. August 25, 2020. You’ll be able to interact with them at Hot Chips. But we work with developers when designing these chips so that their needs are met. RT @anandtech: Today Imagination is announcing the new B-Series GPU IP, adopting a new innovative "decentralised" multi-GPU approach to sca…, @techbiznerd @flomarquard @jcfrick @maltekir @RafaelZeier @Apfelfunk Es ist ja auch abhängig ob Apple eine ähnliche… https://t.co/VrVPvrLQ7a. Featuring up to 96-cores with 4-threads/core, ThunderX3 can deliver a total compute power of 384 threads/socket. Lots of work between AMD and TSMC to hit our targets and what we needed. General: chair@hotchips.org Sun-Tues, August 16-18, 2020 Increased TLB.  It's significantly more efficient than the PC. They were all BGA. iPhone 12 mini The first virtual Hot Chips is on the books! Better infrastructure and fabric control, 01:03PM EDT - Ice Lake: A Balanced CPU for All Server Usages. Hot Chips 2020 is scheduled for August 16th to August 18th. Despite a few relatively minor technical glitches, the program held to the high standards of Hot Chips. Email requests for cancellations must be received by HOT CHIPS on or before 11:59 PM Wednesday, August 12, 2020, and are subject to a $25 processing fee. Hot Chips 2020 Live Blog: Next Gen Intel Xeon, Ice Lake-SP (9:30am PT) by Dr. Ian Cutress on August 17, 2020 11:15 AM EST. Now no longer needed, reduces latency by 3x, 12:56PM EDT - Latencies on bottom right of slide, 12:57PM EDT - AVX512 frequency is low compared to SSE - now some improvements, 12:57PM EDT - Better power analysis of specific AVX512 instructions, 12:57PM EDT - AVX512 now has smarter mapping between instructions and maps, 12:57PM EDT - 3 new power levels for AVX512, 12:58PM EDT - For specific instructions, end up with better frequency for 256-bit and 512-bit instructions, 12:58PM EDT - Provides software writers more incentive to use AVX-512, 12:59PM EDT - SST-PP: Performance Profile, 01:00PM EDT - Select Ice Lake SKUs will have Intel SST enabled, allowing customers to change the performance profile of the CPU based on cooling or requirements, 01:00PM EDT - Dynamically adjusted at runtime, 01:02PM EDT - Wrap up - Sunny Cove in Xeon on 10nm. 2nd-gen Cerebras Wafer Scale Engine, Alibaba RISC-V and NPU, 3rd-gen Google TPUs, 4096-core RISC-V Manticore, Marvell ThunderX3, and ARM Cortex-M55 look interesting. I think after PS4 pro fan noise issues Sony decided to have more capable cooling solution to avoid such scenario. Never mind Cooper Lake, Intel is keen to promote its next generation Xeon Scalable processor line. We might get some insight as to how the company is working with other departments inside Alphabet – it has been cited that Deepmind has used its algorithms to increase the efficiency of cooling inside Google’s datacenters, for example. Hot Chips 2020. probably the main benefit of having larger volume is having place for larger heat sink which by itself helps enormously with dissipation see for example the 3 slots GPUs they do not usually have better or bigger fans but they do have much larger heat sink which helps with cooling enabling the fans to run significantly lower RPM for the same performance (compared to 2 slots designes) lowering the overall noise produced. 09:33PM EDT - Q: Coherency CPU and GPU? The second talk of the session is from Cerebras, known famously for creating its Wafer Scale Engine (WSE) for machine learning. I just don't see how it could fit (besides sideways) and I don't see how that would be beneficial (sideways) because the system has to work vertical and horizontal. https://t.co/UpaRQMEzLe, @borg17 @momomo_us @AMD None of the Stoney Ridge APUs made it to the AM4 desktop socket. Presentations are solicited in early January.2021. While keeping data private, their processor and software stack targets real-time compute, portability as well as continuous learning from real-world data. The final talk in a very long day is from Microsoft, about the Xbox Series X system architecture. Hot Chips 2021 – The conference is usually held in the last half of August in the San Francisco Bay Area. First time trying to use… https://t.co/vPGO9DdMWB. ), 12:47PM EDT - TME using AES-XTS 128-bit, enabled by BIOS, 12:47PM EDT - When enabled, entire memory is encrypted. The ability to train a model across a supercomputer, like an NVIDIA DGX, or across across a large cluster, like a TPU pod, is essential in order to get the appropriate linear speedups that using multiple units of hardware requires. Registration: registration@hotchips.org We needed the GPU to have a ton of bandwidth. Volunteering: volunteer@hotchips.org 09:13PM EDT - MS created Audio engines - 3 engines, CFPU2, MOVAD, LOGAN, 09:13PM EDT - CFPU2 for audio convolution, FFT, reverb, 09:14PM EDT - such as Project Acoustics to model 3D audio sources, 09:14PM EDT - MOVAD - hyper real-time hardware audio decoder, 09:14PM EDT - >300x channels decode at once, 09:14PM EDT - best trade off codec, so made in hardware, 09:15PM EDT - HW realtime real-time matched to decode based on sampling, 09:15PM EDT - Logan is offering also better offload in traditional modes, 09:15PM EDT - HSP/Pluton: Root of trust, crypto, SHACK (crypto keys), 09:15PM EDT - MSP supports 5 GB/s high-bw crypto on the SSD, 09:16PM EDT - DRAM to SSD balance needed for refill, 09:16PM EDT - Load times are always increasing unless SW-to-DRAM bw increases, hence NVMe SSDs, 09:17PM EDT - New metadata for texture portions to pre-load texture caches, 09:17PM EDT - Manages data locations ahead of developer, 09:18PM EDT - Distinct savings for most detail texture maps savings, 09:18PM EDT - Lossless MS XVA 2:1 compression, 09:19PM EDT - Need big GPU - get the tech out of the way, 09:19PM EDT - Need raw ops/second increase within PPA and cost, 09:19PM EDT - 26 active dual CUs (52 CUs), 09:20PM EDT - single geometry supports primatives, 09:20PM EDT - Dual stream multi-core command processor, 09:20PM EDT - single cycle issue rate to reduce stalls, 09:21PM EDT - CUs have 25% better perf/clock compared to last gen, 09:21PM EDT - GPU Evolution: FLOPS have outpaced mem space and BW, 09:21PM EDT - Screen pixels has increased in th emiddle, 09:22PM EDT - How to fill pixels better without blowing power budget, 09:22PM EDT - 10-30% perf gain for tiny area cost, 09:24PM EDT - Previously very slow to enable, 09:24PM EDT - Two new HW structures for tile-by-tile management for in-DRAM textures, 09:26PM EDT - Tilemaps should stay on die for best latency, 09:27PM EDT - SFS: 60% IO/Mem savings for small die area cost, 09:27PM EDT - Not a complete replacement - RT can be applied selectively based on traditional models, 09:29PM EDT - Two virtualized command streams - two VMs, 09:29PM EDT - 32b HDR rendering, blending display, 09:29PM EDT - Optimized games. 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